The present invention relates to an integrated capacitance multiplier circuit, and specifically to a ramp generator with a relatively long time constant that may be entirely integrated in a monolithic form. The circuit is able to provide a time constant in the order of several hundreds milliseconds, without requiring large capacitances that would be difficult to integrate and is useful in a large number of applications.
An ever increasing number of functions that are implemented in an integrated circuit (with the consequent limitation of the number of pins available)has led to the development of circuits that require a minimum number of externally connected components.
Notably parameters or functions that may be entirely integrated with increasing difficulty are relatively large time constants, for example on the order of several hundreds of milliseconds, which normally entail the use of large capacitances that are hardly integratable.
So-called capacitance multiplier circuits that can be fully integrated have been known for a long time. They commonly employ an operational amplifier, capable of controlling the charge current, necessarily of an extremely small value, of an integrated capacitor. A capacitance multiplier circuit, having improved characteristics of precision and thermal drift, is described in the European patent application No. 92830419.5, filed on Jul. 28, 1992, by the instant Applicant.
Capacitance multiplier circuits based on an operational amplifier are relatively complex and require a non-negligible area of integration.
A similar function may also be implemented by employing a simple constant current generator and a circuit capable of dividing the current by a factor in the order of thousands. Such circuits may be implemented by employing a plurality of cascaded current dividers, realized by current mirrors employing transistors of different size. A circuit of this kind, capable of achieving a ramp slope of about 100 V/sec with an integrated capacitance (C) of 10 pF, employing an easily integratable current generator capable of delivering a current of about 10 .mu.A, is shown in FIG. 1.
In the reported example, it is necessary to divide the current Ir by a factor equal to 10,000. As shown in FIG. 1, the circuit may employ four cascaded current mirrors (current dividers), each dividing the current by 10.
A circuit of this type, is less burdensome than a capacitance multiplier based on the use of an operational amplifier, but still requires a non-negligible area of integration and the leakage currents of the tubs (corresponding to the base region of a transistor) within which the large size transistors are found and the substrate of the integrated circuit may assume a value that is comparable with the current I.sub.2 (of about 1 nA) that must be delivered to the integrated capacitance C. At high temperature, the capacitance C may not charge at all.
Also an equivalent circuit of that depicted in FIG. 1, but implemented with NPN transistors instead than with PNP transistors would not provide any significant improvement.
The main aim of the present invention is to provide a ramp generator or a capacitance multiplier that can be fully integrated in a monolithic form while employing a reduced number of transistors that may have the minimum process size.
It is a further object of invention to provide as low ramp generator or capacitance multiplier having reduced area requirements and provided with means for compensating the leakage current of the tubs wherein the transistors that compose the circuit are formed, in order to ensure reliability of the circuit also at a high temperature of operation.
Basically, the circuit of the invention rests on the principle of employing the voltage drop across a number N of directly biased junctions for biasing a number N+k of junctions, where k an integer different from 0, and employing the current flowing through said N+k junctions for charging an integrated capacitance. The N, directly biased junctions are realized by an N number of transistors connected in cascade in a Darlington configuration, functionally connected between a reference current generator and a capacitor to be charged through a series of N+k diodes (junctions). The diodes are directly biased and functionally connected between the same reference current generator and the capacitor, schematically in a parallel arrangement with the cascaded Darlington configured transistors.
All transistors and diodes (or diode configured transistors) may have the minimum size that is allowed by the fabrication process of the integrated circuit.
It may be shown that the charge current of the integrated capacitance, which flows through the series of diodes, is inversely proportional by a factor given by the current transfer ratio (h.sub.FE) of the N transistors used, in a common-emitter configuration, elevated at a power given by the ratio N/N+k (h.sub.FE.sup.N/N+k).
Using an integrated capacitance of about 10 pF, ramp slopes of about 100 V/sec may be easily achieved with only three, Darlington configured cascaded transistors and four diodes (diode-configured transistors). The charge current of the integrated capacitance that flows through the four diodes is given, in first approximation, by the product of the current generated by the current generator, elevated at a power 3/4, with the saturation current (Is) of the transistors used at a power of 1/4, divided by h.sub.FE.sup.3/4, that is: ##EQU1##
The circuit of the invention may also be implemented in different ways, for example in a way suitable to untie the value of the charge current from the h.sub.FE parameter of the transistors used and/or compensate for non-negligible leakage currents, at a high temperature of operation.